Packet switching and processing architectures

Code 145II
Credits 6

Learning outcomes

Objectives
The course presents the main network switching architectures, with particular focus on packet switching architectures. After a brief introduction to the notions of circuit and packet switching, the course will focus on the main schemes of packet switching together with their performance and possible issues. Then, the course will deal with packet lookup and classification by presenting main algorithms currently in use. Finally, the course addresses the topic of traffic measurements and monitoring by introducing the main probabilistic techniques (mainly Bloom filters and their variations) to improve performance on high-speed links.
Syllabus
1) Basics on switching paradigms (circuit/packet switching)
2) Switching fabrics
a. Basic properties of Interconnection Networks
b. Multistage Networks
c. Clos Networks
i. Strictly and Rearrangeably non blocking networks
ii. Recursive construction of Clos networks
d. Self-routing (Banyan) Networks
3) Packet switching architectures
a. Output Queued Switches (OQ)
i. Average delay and maximum throughput
b. Input Queued Switches (IQ)
i. Head Of the Line blocking (HOL)
ii. Virtual Output Queueing
iii. Scheduling (MWM, MSM, etc.)
c. Combined Input-Output queueing (CIOQ) and OQ emulation
4) Packet Lookup and Classification
a. Exact/Prefix match lookup algorithms
i. Unibit and MultibitTrie
ii. Lulea-Compressed Tries
iii. Tree bitmap
b. Mono/Multi dimensional packet classification
5) •Traffic Measurements/Monitoring
a. Packet capturing
b. On-the-wire packet processing
c. Probabilistic techniques for high performance monitoring applications

Exam consists of an oral colloquium including the discussion on a simple project that will be assigned during class time.